By itself, make knows already that in order to create a .o file,
it must use cc -c on the corresponding .c file. These rules
are built into make, and you can take advantage of this to shorten your
Makefile. If you just indicate just the .h files in the
dependency line of the Makefile that the current target is dependent on,
make will know that the corresponding .c file is already
required. You don't even need to include the command for the compiler.
This reduces our Makefile further, as shown:
OBJECTS = main.o hello.o factorial.o
hello: $(OBJECTS)
cc $(OBJECTS) -o hello
hellp.o: functions.h
main.o: functions.h
factorial.o: functions.h
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Make uses a special target, named .SUFFIXES to allow you to
define your own suffixes. For example, the dependency line:
tells make that you will be using these special suffixes to make your
own rules.
Similar to how make already knows how to make a .o file from a
.c file, you can define rules in the following manner:
.foo.bar:
tr '[A-Z][a-z]' '[N-Z][A-M][n-z][a-m]' < $< > $@
.c.o:
$(CC) $(CFLAGS) -c $<
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The first rule allows you to create a .bar file from a .foo file.
(Don't worry about what it does, it basically scrambles the file.) The second
rule is the default rule used by make to create a .o file from a
.c file.
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